For higher integration and higher capacity of a nonvolatile semiconductor memory device, it is necessary to reduce design rules. In order to reduce the design rules, enhanced micro fabrication of wiring patterns or the like is needed. This, however, requires an extremely high level of fabrication technique, so that the reduction of the design rules has become increasingly difficult.
Accordingly, nonvolatile semiconductor memory devices having three-dimensional structures have recently been suggested for higher integration of memory cells.
A common feature of these nonvolatile semiconductor memory devices is that a fin type stacked layer structure is obtained by a semiconductor substrate and memory strings. The memory strings are stacked in a first direction perpendicular to the surface of the semiconductor substrate, and extend in a second direction parallel to the surface of the semiconductor substrate. The memory strings comprise memory cells connected in series in the second direction. One end of the fin type stacked layer structure in the second direction is connected to a beam extending in a third direction perpendicular to the first and second directions. The beam has, for example, a structure in which semiconductor layers and insulating layers are alternately stacked, and functions to prevent the collapse of the fin type stacked layer structure. A function of selecting one of the memory strings is added to a part of the beam.
According to such a structure, theoretically, integration can be enhanced by the increase of the number of stacked memory strings and by the reduction of the fin width (width in the third direction) of the fin type stacked layer structure.
However, both the semiconductor layers that constitute the memory strings and the semiconductor layers that constitute the beam are made of, for example, monocrystalline Si. In this case, if no resistance reduction technique is applied to these semiconductor layers, memory characteristics deteriorate due to the rise of the resistance value (wiring resistance) of the semiconductor layers. This problem becomes more obvious when amorphous Si or polycrystalline Si is used in the semiconductor layer for cost reduction.